(1) Field of the Invention
The present invention relates to the manufacture of integrated circuits in general, and in particular, to a copper process integration in the forming of copper interconnections with improved adhesion and resistance to electromigration.
(2) Description of the Related Art
In the manufacture of semiconductors, the use of copper (Cu) in interconnection metallurgy systems has long been considered as an alternative metallization material to aluminum (Al) and Al alloys due to its low resistivity and ability to reliably carry high current densities. However, its use has presented many problems, such as the possibility of diffusion into the semiconductor substrate, the low adhesive strength of Cu to various insulating layers and the difficulties inherent in masking and etching the blanket Cu layer into intricate circuit structures. In particular, the low adhesive strength of Cu to dielectrics can cause serious reliability problems in integrated circuits. In its simplest form, for example, a trench or groove of desired shape, depth and length can be formed in an insulator, and then filled with copper, as will be described in more detail below. Unless the inside walls of the trench are treated properly, Cu will not adhere with the attendant problems of peeling, delamination, and so on. Furthermore, copper will diffuse into the surrounding dielectric causing other reliability problems. To prevent these problems, it is common first to deposit a lining inside the trench prior to depositing copper. It is disclosed later in the embodiments of the present invention a method of forming a barrier lining as well as a Cu seed layer to improve the strength of copper adhesion, limit the diffusion of copper into surrounding materials and alleviate electro-migration as known in the art.
Aluminum alloys are the most commonly used conductive materials. However, with the advent of very and ultra large scale integrated (VLSI and ULSI) circuits, the device dimensions have been continually shrinking. Thus, it has become more and more important that the metal conductors that form the interconnections between devices as well as between circuits in a semiconductor have low resistivities for faster signal propagation. Copper is often preferred for its low resistivity- about 40% less than that of aluminum- as well as for resistance to electromigration and stress voiding properties. Unfortunately, however, copper suffers from high diffusivity in common insulating materials such as silicon oxide, and oxygen-containing polymers. This can cause corrosion of the copper with the attendant serious problems of loss of adhesion, delamination, voids, electromigration, and ultimately a catastrophic failure of the circuitry.
Conventionally, the various metal interconnect layers in a semiconductor substrate are formed separately, and serially. First, a first blanket metal is deposited on a first insulating layer and electrical lines are formed by subtractive etching of the metal through a first mask. A second insulating layer is formed over the first metallized layer, and the second insulating layer is patterned with holes using a second mask. The holes are then filled with metal, thus forming metal columns, or plugs, contacting the first metal layer. A second blanket metal layer is formed over the second insulating layer containing the columnar plugs which now connect the upper second metal layer with the lower first metal layer. The second metal layer is next patterned with another mask to form a set of new electrical lines, and the process is repeated as many times as it is needed to fabricate a semiconductor substrate. It will be observed that patterning, that is, photolithography and etching of metal layers to form the needed interconnects constitute a significant portion of the process steps of manufacturing semiconductor substrates, and it is known that both photolithography and etching are complicated processes. It is desirable, therefore, to minimize such process steps, and a process known as dual damascene, provides such an approach. The term xe2x80x98damascenexe2x80x99 is derived from a form of inlaid metal jewelry first seen in the city of Damascus. In the context of integrated circuits it implies a patterned layer imbedded on and in another layer such that the top surfaces of the two layers are coplanar.
In a single damascene process, grooves are formed in an insulating layer and filled with metal to form conductive lines. Dual damascene shown in FIG. 1b takes the process one step further in that, in addition to forming the groove (20) of a single damascene, conductive hole opening (40) is also formed in the insulating layer. The resulting composite structure of groove and hole are filled with metal simultaneously. The process is repeated as many times as required to form the multi-level interconnections between metal lines and the holes formed in between. Contact holes are formed directly over the substrate where the metal in the hole contacts the surface of the substrate, while the via holes are formed between metal layers. With copper as the conductive metal in groove (20) and/or opening (40), copper diffuses (shown with arrows (5) in the same Figures) into the surrounding dielectric material (30), causing electrical shorts with other neighboring lines (not shown), or into the underlying silicon (10), causing transistor poisoning where junction leakage occurs with reduced channel mobility in the transistor, thereby destroying the device.
In prior art, methods have been devised to prevent copper diffusion by employing a barrier between the copper interconnect and adjacent materials of a semiconductor device. FIG. 1b shows a conventional substrate (10), upon which a barrier (60) and a copper layer (70) are formed. Barrier (60) comprises a material which impedes the diffusion of copper from copper layer (70) into the underlying substrate (10). However, barrier (11) is not perfect as it has micro-defects such as pinholes (67) or voids in the film, and the barrier further comprises a number of grain boundaries illustrated as (61), (63), (65) and (69). Micro-defect (67) along with grain boundaries, act as weak spots in the barrier, permitting copper form copper layer (70) to diffuse (5) through to the underlying substrate (10). As shown, within micro-defect region (67) the copper of copper layer (70) comes into direct contact with substrate (10). Substrate (10) comprises silicon and silicon dioxide, through which copper rapidly diffuses from the micro-defect in the barrier, particularly at elevated temperatures. Similarly, copper rapidly diffuses along grain boundaries of the barrier when subjected to elevate temperatures.
It is common practice that to better isolate copper layer (70) from the underlying substrate (10), the thickness of barrier (60) is increased. However, increasing the thickness of the barrier also increases the resistance of the resulting copper interconnect as illustrated in FIG. 1c FIG. 1c shows a cross-section of a substrate (10) upon which an electrical interconnect comprising copper layer (90) and barrier (80) have been formed in a dielectric layer material (95). As shown, the thickness of barrier layer (80) is large in comparison to the thickness of copper layer (90). It is necessary for barrier (80) to be thick enough to adequately prevent diffusion (5) of copper from copper layer (90) into either dielectric material (95) or substrate (10).
Forming a thicker barrier reduces copper diffusion through micro-defect because the defects are more likely to be incorporated into the bulk of the barrier, thereby reducing diffusion paths through the defect. In addition, while a thicker barrier may still comprise grain boundaries leading from the upper to lower surface of the barrier, these boundaries are necessarily longer. Because the grain boundaries are long, it takes a longer time for copper to diffuse throughout the length of these longer grain boundaries. However, increasing the barrier thickness while maintaining the overall width of the interconnect increases the total resistance of the electrical interconnect due to the reduction in volume that the low resistance copper material can occupy. The barrier materials, such as nitrides, are invariably much more resistive than copper. The total width of the interconnect could be increased to counteract the increased resistance, but doing so would reduce the density of the integrated circuit. As result, the speed at which the integrated circuit operates is reduced.
Jain of U.S. Pat. No. 5,821,168 discloses a process for forming a semiconductor device in which an insulating layer is nitrided and then covered by a thin adhesion layer before depositing a composite copper layer. This process does not require a separate diffusion barrier as a portion of the insulating layer has been converted to form a diffusion barrier film, so that the over-all thickness of the barrier film is relatively small.
Sandhu, shows a copper plating process in U.S. Pat. No. 5,662,788 in which he uses a single electro-deposition step to reliably form both the metallization layer and to full the via holes. Another electro-deposition method is disclosed by Gilton, et al., in U.S. Pat. No. 5,151,168 for copper metallization of integrated circuits. First, a thin conductive barrier layer is sputtered on a wafer. The wafer is then transferred to an electrolytic bath. Metallic copper is deposited on the barrier layer to form the desired interconnect.
On the other hand, a self-contained unit for forming copper metallurgy interconnection structures on a semiconductor substrate is shown by Chen, in U.S. Pat. No. 5,723,387. The unit has an enclosed chamber with a plurality of apparatus for performing wet processes, including electroless metal plating and planarization. The unit provides a way of reducing the number of times the wafer is transferred between he wet process steps that requires environmental cleanliness and dry very clean processes steps.
Dubin, et al., disclose a method for reducing oxidation of electroplating chamber contacts and improving uniform electroplating of a substrate in U.S. Pat. No. 5,882,498. This is accomplished by preplating the contacts or fingers that manipulate substrates before loading the substrates onto the contacts.
In addition to the adhesion and diffusion problems associated with copper interconnects in general, there are problems that are encountered with electroplating itself. Specifically, copper oxide that normally forms on a copper seed layer will prevent successful electroplating thereon. It is disclosed in the instant invention an integrated method of reducing copper oxide in order to provide improved electroplating of copper interconnects.
It is therefore an object of the present invention to provide a method to improve copper process integration in the forming copper interconnects in integrated circuits.
It is another object of the present invention to provide a method of reducing copper oxide prior to electroplating copper in forming copper interconnects in integrated circuits.
It is yet another object of the present invention to provide a method for well-controlled electrochemical deposition (ECD) of copper for solid filling of a damascene trench.
These objects are accomplished by providing a semiconductor substrate having a substructure comprising devices formed in said substrate and a metal layer formed thereon; forming an inter level dielectric (ILD) layer over said substrate; patterning and etching said ILD layer to form a trench with inside walls therein; performing physical or chemical vapor deposition (PVD/CVD) of a diffusion barrier layer over said substrate including over said inside walls of said trench; forming a metal seed layer over said substrate including over said diffusion barrier layer; performing oxide reduction over said metal seed layer; forming a metal layer over said substrate including over said metal seed layer; and removing excess metal layer from said substrate.